Accompanying the compactization of electronic equipment, the miniaturization of semiconductor chips and the parts, and making the terminals have narrow pitches, reduction in packaging area of a printed wiring board (wiring substrate) and making wiring be precise have been progressed. Further, with respect to information-related equipments, to address a broadband signal frequency, there is high demand to make circuits connecting between parts short. Therefore, in order to achieve a high density and high performance, making a printed wiring board multi-layered is an indispensable technique.
With respect to a multi-layer board, a circuitry (interlayer conductive portions) for electrically connecting between layers, which was not in a conventional circuit board, is the key technology. At a multi-layer board base material structuring the respective layers of the multi-layer board, through holes are provided at an insulating layer, and due to conductors being plated along the inner wall surfaces of the through holes, one side surface and the other side surface of the multi-layer wiring base material are electrically connected.
IBM provides an SLC (Surface Laminar Circuitry) which is a representative build-up multi-layer board, and according to a method thereof, a part of the insulating layer of the multi-layer board base material is eliminated by photolithography process by using a photosensitive resin, a laser beam machining, or the like, and interlayer conductive portions for connecting between the layers are formed by plating (for example, “Build-up multi-layer printed wiring board technology” by Kiyoshi Takagi; published by THE NIKKAN KOGYO SHINBUN, LTD.).
Conductive connection of wiring by using plating has the advantage that fine circuitry can be connected so as to be conductive at a low resistance. However, because the manufacturing process is complex, and the man-hour is large, the cost is increased, and it becomes a factor of limiting the uses of a multi-layer board.
In recent years, as a low-priced interlayer connecting method in place of plating, a multi-layer board using a conductive resin which is typical of an ALIVH (Any Layer Interstitial Via Hole) board of MATSUSHITA GROUP or a B2 bit (Buried Bump Interconnection Technology) of TOSHIBA GROUP has been put to practical use, and the uses of the multi-layer board has been started to be rapidly expanded (for example, in Japanese Patent Application Laid-Open No. H6-302957, Japanese Patent Application Laid-Open No. H9-82835, and “Build-up multi-layer printed wiring board technology” by Kiyoshi Takagi: published by THE NIKKAN KOGYO SHINBUN, LTD.).
According to the ALIVH, as shown in FIGS. 1A through 1H, by using an insulating plate 101 made from prepreg as a starting material, and via holes 102 passing through the one side surface and the other side surface of the insulating plate 101 are provided by using a laser, and interlayer conductive portions 103a are formed by filling conductive pastes 103 into the via holes 102 by a printing process. Due to this operation being carried out on desired regions, an insulating base material 104 having the interlayer conductive portions 103a is formed. Further, copper foils 105 are compressively bonded respectively to the one side surface and the other side surface of the insulating base material 104, and desired wiring patterns (copper foil circuitry) 106 are formed by etching. With respect to the one side surface and the other side surface of the insulating base material 104 obtained in this way, insulating base materials 107 having the same structure as the insulating base material 104, and copper foils 108 are respectively compressively bonded. A multi-layer board 100 is formed by a build-up process in which forming of a wiring pattern 109 on the copper foil 108 after the compression bonding is repeated.
Other than the method of the ALIVH, as used in the manufacturing method of the SLC, via holes are can be formed by carrying out exposure and development on an insulating layer a desired number of times by using a photosensitive resin, and a disused resin is eliminated by chemical etching or dry etching can be applied.
The manufacturing method of a multi-layer board which uses conductive paste is in low-priced, and on the other hand, there are some disadvantages that the electrical resistance of the conductive paste is greater than the plating used in the build-up process, the contact resistance with a copper foil circuitry is unstable, and the like. However, those are getting to be gradually solved.
With respect to a wiring board, such as a multi-chip module or the like, into which a bare chip assembled, there is the trend that the thickness of one layer structuring the multi-layer board is reduced accompanying making wiring have high density. Due to this reduction in a layer thickness, as a single insulating film, flexures or wrinkles easily arise, and it is difficult to ensure a dimensional stability.
In consideration of this problem, as the manufacturing method of the multi-layer board using conductive paste for interlayer connection, as shown in FIGS. 2A through 2F, there is a manufacturing method by using a film 201 (a starting material) which has an insulating layer 204 and a copper foil 202 on one side of the insulating layer 204. In accordance with the manufacturing method, a multi-layer board 200 is formed due to a plurality of multi-layer wiring base materials 207 being bonded to each other, and being colaminated one another so that the base materials 207 are fixed to one another. A desired wiring pattern (copper foil circuitry) 203 is formed by etching on the copper foil 202, and via holes 205 are opened at the insulating film layer 204, and interlayer conductive portions 206a are formed by filling conductive pastes 206 into the via holes 205 (however, via holes are not provided at a base material 208 which performs as the bottom layer) (for example, Japanese Patent Application Laid-Open No. 2002-353621). This method is called a colaminating press process.
In accordance with the colaminating press process, a copper clad base material (a film with single-sided copper foil) which is comprised of a resin film performing as an insulating layer and a copper foil being provided on top of the resin film (insulating layer) and which performs as a conductive layer is used as a starting material. Therefore, the rigidity of the film is improved, and a high dimensional accuracy can be maintained.
Moreover, according to the colaminating press process, because internal circuitry is formed before the colaminating operation, the multi-layer board which is manufactured by colaminating press process can be prepared for a shorter time and can be manufactured at a higher yield ratio than a multi-layer board manufactured by the build-up process. However, in order to obtain an accuracy which is the same as the build-up process, because colaminating press process is carried out after the multi-layer board base material structuring the respective layers of the multi-layer board is formed in the colaminating press process, it is necessary to high-precisely align the respective multi-layer board base materials each other.
Heretofore, to position layers with a high degree of accuracy in the colaminating press process, a pin alignment process in which a pin passes through a pinhole being provided at a predetermined portion is used. In accordance with the pin alignment process, to enhance the accuracy of the method, it is important to accuracy process the pinhole, and a clearance between the pinhole and the pin made small. However, there is a limit to such an accuracy of the layer to layer positioning, and as compared with the build-up process, the accuracy is inferior thereto. Therefore, even if a board at which a minute circuitry (a fine printed circuitry) has been formed in advance is prepared, alignment of these boards to make a multi-layer wiring board is difficult. In addition, the minute circuitry means a circuitry, wherein the wiring density of the conductor forming the circuitry is very high.
On the other hand, with respect to the multi-layer board, such as SLC, manufactured by the build-up process, because laminating and formation of a circuitry are repeated in order at one layer by one layer, alignment of the circuitry of the adjacent multi-layer board base material, the via holes, the circuitry at the surfaces depends on an accuracy of alignment when a photolithography is carried out. Generally, in the build-up process, the accuracy of registration is higher than that of the multi-layer board formed by the colaminating in which circuitry which have been laminated in advance are aligned and bonded to each other. Consequently, the build-up process is used for many multi-layer boards to which semiconductor chips are directly bonded thereto. However, in the multi-layering by the build-up process, as described above, the manufacturing process is complex, and the man-hour is large, and it highly costs.
The present invention has been made in order to solve the problems as described above, and an object of the present invention is to provide a multi-layer board in which a minute circuitry is formed at the surface layer and semiconductor elements having a narrow pitch can be mounted without loosing the advantage of colaminating process, and a manufacturing method thereof.